Novel gate structure and method of forming the gate dielectric with mini-spacer

ABSTRACT

A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates generally to methods of fabricating a gatedielectric and a mini-spacer, and more particularly, to methods ofpatterning gate structures with high-k gate dielectric films andmini-spacers in the fabrication of semiconductor devices and integratedcircuits.

(2) Description of the Prior Art

The current generation ultra large-scale integrated (ULSI) circuits usepredominantly field effect transistor (FET) devices, having poly-silicongate electrode, silicon dioxide gate dielectric, and self-alignedsource/drain regions. Typical process of fabricating an FET consists ofgrowing a thin gate silicon dioxide on a silicon substrate and thenforming the poly-silicon gate electrode. Source/drain (S/D) regions arethen formed adjacent to the gate electrode, which then defines the FETgate length as the distance under the poly-silicon gate between the S/Dregions. The gate length and the control of gate length is critical,particularly as channel lengths continue to decrease to achieve highdevice densities, since short channel effects (SCE) can occur in thedevice. SCE effects become predominant since band-gap and junctionpotentials cannot be scaled with channel length, being dependent on thesubstrate material (i.e. silicon).

Fabrication of the gate electrode structure is critical in achievingoptimum performance of the MOSFET (metal-oxide-silicon field effecttransistor) device. The gate stack, consisting of the gate electrode andthe gate dielectric, essentially determines the operating speed andreliability of the device.

Although silicon dioxide has been the dielectric of choice for manyyears because of ease of forming the film and patterning it, high-krefractory metal oxides are being increasingly experimented in recentyears. The motivation is that high-k gate dielectric films reduce theequivalent gate oxide thickness between the gate metal and thesubstrate, thereby increasing device performance. If silicon dioxide hasto be used in ULSI devices with short channel length, it needs to bequite thin to achieve large capacitance values and formation ofnanometer range, high quality oxides without defects is quite difficultif not impossible. Several gate structures with high-k gate dielectrichave been proposed in prior art. However, patterning of high-k films,unlike the conventional silicon oxides or nitrided oxides, is difficultfor two main reasons: i) plasma etching of these films that do noteasily form volatile reaction products requires high self-developed orapplied bias voltages will cause device damage of the silicon surface ofthe transistor and ii) alternatively, non-damaging wet etching processesresult in poor dimensional control of the FET channel length and areprone to etch residues that are hard to remove during post-processingsteps.

U.S. Pat. No. 5,447,874 describes a method of producing devices withimproved gate length control, eliminating contamination induced surfacedamage, leakage problems without increasing processing steps. A gateopening is anisotropically etched in an oxide layer, creating a reversegate metal image that has low gate length variability. Dual metal gateis then deposited and the excess gate metal is removed and the topsurface of the gate planarized using chemical mechanical polishing. Theremaining oxide is then removed. The patent refers to a dual metal gatewith a conventional silicon dioxide gate dielectric film.

In U.S. Pat. No. 5,940,698, a device with a high performance gatestructure and a fabrication process is described. According to theprocess disclosed, a gate insulating film is deposited over a substrate,a diffusion barrier layer is then formed over the gate-insulating layer,and a trench is etched in the diffusion barrier layer. In the trench, ametal gate electrode is formed. Although the high-k materials likecobalt niobate, barium strontium nitrate (BST), and tantalum oxide areproposed, the process described is quite complex and it is very likelythat etch residues will be left on the silicon substrate when etchingthe high-k film within the gate trenches and around the gate structure,as previously discussed.

U.S. Pat. No. 5,960,270 describes a process of forming ametal-gate/metal-oxide/semi-conductor MOS transistor with self-alignedsource and drain electrodes formed before defining the metal gate.Although high-k metal oxides like TiO₂ and Ta₂O₅ are mentioned as a partof a composite dielectric gate (e.g. grown oxide/deposited high-kmaterial), no specific process is described or taught on how to patternhigh-k films without the problems associated with post-etch residues.

U.S. Pat. No. 5,766,998 describes a method of forming reverseself-aligned FETs (field effect transistors) with gate electrode ofsub-quarter micrometer dimensions that exceed the lithographicresolution limit with the use of polymer sidewall spacers. The processdescribed includes forming a stack of titanium layer, and N⁺ doped firstpoly-silicon layer, and a silicon nitride layer over the device regions.Non-volatile polymer sidewall spacers are then formed on the sidewallsof the first openings. The sidewalls and the photo-resist together actas a mask for selectively etching the said stack down to the substrateand form the second opening to define the FET channel. A gate oxide isgrown on the substrate in the channel opening. The gate dielectric filmis a conventional silicon dioxide grown by thermal oxidation.

In U.S. Pat. No. 6,033,963, a method is described to form a metal gatefor a CMOS device, using a replacement gate process. According to theprocess, a dummy gate oxide and a poly-silicon gate electrode layer areformed and patterned to form a a dummy gate. Lightly doped source anddrain regions are formed using dummy gate as implant mask. After formingsidewall spacers, source and drain regions are formed and annealedTungsten layer is then selectively deposited on the exposed siliconsurfaces. Blanket dielectric layer is then deposited and planarized,stopping on the tungsten layer. The tungsten overlying the dummy gateare removed, thereby forming a gate opening. A gate oxide layer and ametal gate electrode layer are then deposited in the gate opening andplanarized, stopping on the blanket oxide layer. The structure uses aconventional oxide as the gate dielectric.

SUMMARY OF THE INVENTION

Accordingly, it is a primary object of the invention to describe asimple method to form a gate structure with high-k dielectric gate andmini-spacer surrounding the gate.

Another object of the invention is to describe a gate structure withhigh-k gate dielectric and high-k mini-spacer as an integral part of thedevice.

It is yet another object of the invention to describe a damage-free andresidue-free process for forming a high-k gate dielectric andsimultaneously form high-k mini-spacer as part of the gate formingprocess.

Yet another object of the invention is to describe a process for forminghigh-k gate dielectric and mini spacer structure, using a disposabledummy trench structure.

A further object of the invention is to provide an FET device with agate structure having a high-k gate dielectric with improved control ofgate length and an integral mini-spacer.

In accordance with these objectives, a method is described to fabricatea gate structure with high-k dielectric material, a mini-spacer of thesame high-k material, and improved gate length. The high-k gate film ispatterned damage-free and without leaving any process residues. A trenchpattern is formed in a disposable dummy film that is deposited over asilicon substrate. A high-k dielectric film liner is then depositedwithin said trench pattern. The trench, with high-k film as the liner,is then filled with poly-silicon gate conductor. The structure is thenplanarized preferably using chemical mechanical polishing method orother etch-back processes, such that said high-k film on the planarsurfaces of the dummy film is also removed during the planarizing step,thereby leaving the high-k film liner only inside the trenches. Thedummy film around the gate is then removed to leave a structure withmini-spacer of high-k material surrounding the gate. Because the processuses a deposition method to form the high-k gate structure within adummy trench, the gate length is much more precisely defined as comparedto methods using etching process to pattern high-k gate.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, advantages, and details of fabricating a semiconductordevice according to this invention will be more clearly understood fromthe following detailed description taken in conjunction with theaccompanying drawings.

FIG. 1 is a cross-sectional view of the invention, showing a dummy filmand oxide film deposited over a silicon substrate.

FIG. 2 is a cross-sectional view of the invention showing the patterneddummy trench etched in dummy film and oxide film.

FIG. 3 is a cross-sectional view of the invention showing the trenchpattern with a high-k dielectric film deposited on all exposed surfaces.

FIG. 4 is a cross-sectional view of the invention showing a structurewherein the trench pattern is filled with poly silicon which also showsa dimple over the trench.

FIG. 5 is a cross-sectional view of the invention showing the waferafter planarizing the poly-silicon and with high-k film removed fromdummy film surface.

FIG. 6 is a cross-sectional view of the invention showing the final gatestructure after the dummy film has been removed. The entire gatestructure shows the poly gate conductor, high-k mini spacer, and high-kgate dielectric.

FIG. 7 is a cross-sectional view of an FET device showing source/drainregions and the high-k gate structure and mini-spacers of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The process described in the present invention provides a simplifiedmethod to fabricate a gate structure in an FET semiconductor device witha high-k gate dielectric and a mini-spacer, without producing any devicedamage or leaving any process residues. Although in the presentinvention a dummy trench is etched in nitride or organic BARC film, anymaterial that can be easily patterned using conventional wet or plasmaetching process can be used.

Referring now to FIG. 1, there is shown a substrate 10 that is siliconof desired crystallographic orientation in this embodiment having otherparts of the FET device already formed (not shown) in it. A disposabledummy film 20, is then deposited over substrate 10 using standarddeposition methods such as: chemical vapor deposition (CVD), plasmaenhanced CVD (PE-CVD), or spin coating known in prior art. The dummyfilm can be of inorganic type selected from a group of inorganicmaterials comprising silicon nitride, silicon oxy-nitride, silicondioxide, inorganic arc film, amorphous silicon, doped or un-dopedpoly-silicon, silicon-germanium; or of organic type selected from agroup of materials comprising resist, organic anti-reflection film, apolymer, and polyimide. If silicon nitride is used as the dummy film ofchoice to form the trenches in, a thin silicon dioxide film 21 is firstdeposited over substrate 10 to reduce the stress created by the thicksilicon nitride film. The dummy film thickness is kept approximately atthe thickness of the gate structure, of between about 1000-5000° A.Thickness of silicon dioxide used to reduce the stress of nitride filmis normally in the range of about 50-150° A.

Referring now to FIG. 2, there is shown a trench pattern 22 etched inthe dummy films 20 and 21, using standard lithographic techniques andplasma etching process well known in prior art. A photo-resist mask isfirst formed (not shown) over the dummy film and the trench patternformed using a selective plasma etching process such that etching stopson the substrate surface 11. If an inorganic film is used as the dummyfilm, the etching process typically uses gaseous plasma containingpredominantly fluorine species. Examples of such gases are: CF₄, CHF₃,C₂F₆, C₄F₈, NF₃, SF₆. If organic type films are used, the etchingprocess uses gaseous plasma containing predominantly oxygen species.Examples of these gases are: O₂, NO₂, CO₂.

Referring now to FIG. 3, there is shown said trench pattern 22 withhigh-k gate dielectric film 30 deposited on all of the exposed surfaces.High-k film 30 is selected from a group of materials comprisingZr_(x)O_(y), Hf_(x)O_(y), Ta_(x)O_(y), Ti_(x)O_(y), Al_(x)O_(y),Hf_(x)Si_(y)O_(z), and/or Zr_(x)Si_(y)O_(z). Alternatively, gatedielectric film may also be selected from a groups of comprising silicondioxide, silicon dioxide nitrided by decoupled plasma or nitridationprocess, silicon nitride, and/or silicon oxy-nitride. The high-k film,equal to the equivalent gate oxide thickness of about 20-100° A, in therange of about 50-200° A, is then deposited using chemical vapordeposition processes or other deposition methods such as sputterdeposition, known in prior art such that conformal deposition takesplace. Conformal deposition implies near-equal thickness of the film onvertical planes 23, horizontal planes 24, and surface 11. Although inthe preferred embodiment, conformal film of the high-k gate material isused, the film can also be deposited in a partially conformal manner(i.e. thickness on all the surfaces is not equal) as long as the high-kfilm adequately covers the step of the gate trench pattern.

Referring now to FIG. 4, there is shown the trench pattern with thepreferred doped poly silicon gate conductor material 40 deposited insidethe trench and over the entire planar surface. The poly-siliconthickness is so adjusted as to achieve adequate overburden so that thewhole wafer is covered with poly-silicon and the dimples 41 over thetrench patterns are well above the plane of the high-k film on surface24. The thickness of poly-silicon is normally greater than about 2000°A. Although doped poly-silicon is used as the gate conductor in thepreferred embodiment, other silicon-based materials selected from thegroup comprising single crystal silicon, poly silicon, doped silicon,doped poly-silicon, amorphous silicon, and/or silicon-germanium andmetal-based gate conductors such as, tungsten, tungsten nitride,aluminum, Ti_(x)N_(y), Ta_(x)N_(y), copper, WSi_(x), and CoSi_(x) can besuccessfully used.

Referring now to FIG. 5, there is shown the partial structure after thepoly-silicon over the trench pattern has been planarized, preferablyusing chemical mechanical planarization (CMP) or plasma etch backprocesses well know in prior art. Planarization is done such that thehigh-k film on the horizontal surface 24 of the dummy film 20 iscompletely removed during this step. Incomplete removal of high-k filmor residues left on surface 24 transfer themselves on the substrate andresult in process residues when the dummy film is stripped off in alater and final step.

Referring now to FIG. 6, there is shown the final gate structure 50after the dummy film 20 adjacent to the gate structure has been strippedoff using plasma or wet etching process. When the dummy film is of theinorganic type, wet or suitable plasma etching processes selective tothe substrate 10 are used. When the dummy film is of the organic type,organic solvent strip or suitable ashing processes such as oxygenplasma, UV/ozone, or microwave plasma are used. The final structure inFIG. 6, shows the gate conductor of poly silicon 40, high-k gatedielectric 30 b and high-k mini-spacer 30 a surrounding the gateconductor, with the entire gate structure fabricated on siliconsubstrate 10.

FIG. 7 shows the FET device, showing the source 42 and drain 44 regionsand the gate structure of the invention: high-k gate dielectric 30 b,poly-silicon gate conductor 40, and high-k mini-spacer 30 a.

The advantages of the aforementioned invention are:

-   -   a) A gate structure is formed with high-k gate dielectric and        high-k mini spacer, both formed simultaneously without the use        of additional steps.    -   b) A non-etching process is used for forming the high-k gate        dielectric pattern and the mini-spacers, thereby not producing        any etch residues.    -   c) High-k gate structure is patterned without any etch damage        since plasma etching, which is inherently prone to producing        device damage, is not directly used to etch the high-k film.        Only the dummy film patterning uses the plasma etching process.    -   d) High-k gate pattern is formed by a deposition process and not        by plasma etching.

While the invention has been particularly shown and described withreference to the preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the concept, spirit, and the scope of theinvention.

1-9. (canceled)
 10. An FET gate structure comprising high-k gatedielectric on a substrate, gate conductor on said dielectric, and high-kspacer surrounding said gate conductor and gate dielectric.
 11. An FETgate structure according to claim 10, wherein said gate dielectric isselected from the group comprising Zr_(x)O_(y), Hf_(x)O_(y),Ta_(x)O_(y), Ti_(x)O_(y), Al_(x)O_(y), Hf_(x)Si_(y)O_(z), andZr_(x)Si_(y)O_(z).
 12. A gate structure according to claim 10, whereinsaid gate conductor is selected from the group comprising silicon-basedgate material and metal-based gate material.
 13. A gate structureaccording to claim 12, wherein said silicon-based gate material isselected from the group comprising single crystal silicon, poly silicon,doped silicon, doped poly-silicon, amorphous silicon, andsilicon-germanium.
 14. A gate structure according to claim 12, whereinsaid metal-based gate material is selected from the group comprisingtungsten, tungsten nitride, aluminum, Ti_(x)N_(y), Ta_(x)N_(y), copper,WSi_(x), and CoSi_(x).
 15. An FET device comprising a silicon substrate;source and drain regions on said silicon substrate; transistor gatestructure having a gate conductor and a high-k gate dielectric disposedbetween said gate conductor and said substrate; and high-k spacerssurrounding said gate conductor and high-k gate dielectric.
 16. An FETdevice according to claim 15, wherein the said gate dielectric film isselected from the group comprising Zr_(x)O_(y), Hf_(x)O_(y),Ta_(x)O_(y), Ti_(x)O_(y), Al_(x)O_(y), Hf_(x)Si_(y)O_(z), andZr_(x)Si_(y)O_(z).
 17. An FET device according to claim 15, wherein saidgate conductor is selected from the group comprising silicon-based gatematerial and metal-based gate material.
 18. An FET device according toclaim 17, wherein said silicon-based gate material is selected from thegroup comprising single crystal silicon, poly silicon, doped silicon,doped poly-silicon, amorphous silicon, and silicon-germanium.
 19. An FETdevice according to claim 17, wherein said metal-based gate material isselected from the group comprising tungsten, tungsten nitride,aluminium, Ti_(x)N_(y), Ta_(x)N_(y), copper, WSi_(x), and CoSi_(x).